Logic BIST technique

Typical logic BIST system

The test pattern generator (TPG) automatically generates test patterns for application to the inputs of the circuit under test (CUT).The output response analyzer (ORA) automatically compact the output responses of the CUT into a signature. Specific BIST timing control signals, including can enable signals and clocks, are generated by the logic BIST controller for coordinating the BIST operation among the TPG, CUT, and ORA. The logic BIST controller provides a pass/fail indication once the BIST operation is complete. It includes comparison logic to compare the  final signature  with an embedded golden signature, and often comprises diagnostic logic for fault diagnosis. As compaction is commonly used for output response analysis, it is required that all storage elements in the TPG,  CUT, and ORA be initialized to known states prior to self-test, and no unknown (X)values be allowed to propagate from the CUT to the ORA.

# BIST Pattern Generation

There are various methods and approaches have been used to generate test patterns during BIST, LFSR-Linear Feedback Shift Register.

# BIST output response analysis (ORA)

During BIST, for every test pattern that being generated, the CUT produces a set of output values. In order to ensure the chip is fault free, every output values from the CUT for each test pattern will need to compare with the correct output values obtained from the simulations. This is a tedious and time consuming process. Thus, it is necessary to reduce the enormous of circuit responses to a manageable size that can be either store in the chip or can easily compared with the golden response values. For example, a BIST pattern generator in a chip cans produce1million test patterns. If the chip has a total of 100 primary output, at the end of the BIST process, it will generate a total of 1 million output values or 1000000x100= 100millionbitsof output values. With such a huge amount of data, it is very costly and almost impossible to store in the storage or ROM inside a chip
There are several approaches and method can be used for response compaction, such as transition count response compaction, LFSR for response compaction, Modular LFSR response compaction, single-input signature register(SISR) and multiple  input signature register (MISR) used as response compactor.

# Logic BIST Architectures

Several architectures for in corpora ting offline BIST techniques into a design have Been proposed. architectures generally fall into four categories:
(1) those that assume no special structure to the circuit under test,
(2) those that make use of scan chains in the circuit under test,
(3) those that configure the scan chains for test pattern generation and output response analysis, and
(4) those that use the concurrent checking (implicit test) circuitry of the design.

# Circuit under Test (CUT)

For testing purpose sometimes for example we use RAM circuit under test shown in Figure. The system that is to be tested is termed as CUT. It is the circuit of the IC that is going to be checked for any defects after its manufacturing. Any digital design represented in VHDL is used as a CUT.

# BIST Controller

BIST controller coordinates the operations of different blocks of the BIST. Based on the test mode input to the controller, the system either operates in the normal mode or in the test mode. When the TM is1, the system enters the test mode, it gives enable signal to the LFSR which generates the patterns and then it gives enable signal to MISR for the compression of patterns from the RAM. It is the controller which decides for how many cycles the enable need to be made1 based on the length of the scan chains and the input-output size of the RAM.

Block Diagram of BIST Design