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Its ritu here.....

Howz u all.... hope well... now i m going to give you interesting knowledge here's my another blog where i share all the intresting things which i know ... sometimes engineering seems so boring.... but really its not... the things which are interesting and knowledgible too ... can help you enhance your knowledge with joy..

I have another blog where i share my all stuffs  ....

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Logic BIST technique

Typical logic BIST system

The test pattern generator (TPG) automatically generates test patterns for application to the inputs of the circuit under test (CUT).The output response analyzer (ORA) automatically compact the output responses of the CUT into a signature. Specific BIST timing control signals, including can enable signals and clocks, are generated by the logic BIST controller for coordinating the BIST operation among the TPG, CUT, and ORA. The logic BIST controller provides a pass/fail indication once the BIST operation is complete. It includes comparison logic to compare the  final signature  with an embedded golden signature, and often comprises diagnostic logic for fault diagnosis. As compaction is commonly used for output response analysis, it is required that all storage elements in the TPG,  CUT, and ORA be initialized to known states prior to self-test, and no unknown (X)values be allowed to propagate from the CUT to the ORA.

# BIST Pattern Generation

There are various methods and approaches have been used to generate test patterns during BIST, LFSR-Linear Feedback Shift Register.

# BIST output response analysis (ORA)

During BIST, for every test pattern that being generated, the CUT produces a set of output values. In order to ensure the chip is fault free, every output values from the CUT for each test pattern will need to compare with the correct output values obtained from the simulations. This is a tedious and time consuming process. Thus, it is necessary to reduce the enormous of circuit responses to a manageable size that can be either store in the chip or can easily compared with the golden response values. For example, a BIST pattern generator in a chip cans produce1million test patterns. If the chip has a total of 100 primary output, at the end of the BIST process, it will generate a total of 1 million output values or 1000000x100= 100millionbitsof output values. With such a huge amount of data, it is very costly and almost impossible to store in the storage or ROM inside a chip
There are several approaches and method can be used for response compaction, such as transition count response compaction, LFSR for response compaction, Modular LFSR response compaction, single-input signature register(SISR) and multiple  input signature register (MISR) used as response compactor.

# Logic BIST Architectures

Several architectures for in corpora ting offline BIST techniques into a design have Been proposed. architectures generally fall into four categories:
(1) those that assume no special structure to the circuit under test,
(2) those that make use of scan chains in the circuit under test,
(3) those that configure the scan chains for test pattern generation and output response analysis, and
(4) those that use the concurrent checking (implicit test) circuitry of the design.

# Circuit under Test (CUT)

For testing purpose sometimes for example we use RAM circuit under test shown in Figure. The system that is to be tested is termed as CUT. It is the circuit of the IC that is going to be checked for any defects after its manufacturing. Any digital design represented in VHDL is used as a CUT.

# BIST Controller

BIST controller coordinates the operations of different blocks of the BIST. Based on the test mode input to the controller, the system either operates in the normal mode or in the test mode. When the TM is1, the system enters the test mode, it gives enable signal to the LFSR which generates the patterns and then it gives enable signal to MISR for the compression of patterns from the RAM. It is the controller which decides for how many cycles the enable need to be made1 based on the length of the scan chains and the input-output size of the RAM.

Block Diagram of BIST Design

Memory testing

INTRODUCTION

Testing is a process of checking the fabricated chip against manufacturing defects, to determine the presence of a fault in a given circuit, no amount of test can guarantee that the circuit is fault free we carry out testing to validate the circuit. Two types of approaches are used to verify the circuit first is simulation-based approach and the second are the formal method [3]System board, chip, gate switch interconnection, logic function every part is tested. Adding some extra logic such that the memory can test itself whenever the test is enabled is called Design for Testing (DFT). There are some testing issues first one is testing at higher level cost higher, test application time grows exponentially e.g. For a combinational circuit with 60 input we need 2^60 test patterns are required, the third one is the lack of controllability and observability of flip-flops (test generation for sub sequential Circuit is difficult) basic test principal is input patterns are applied to the CUT and output is compared with the previously decided golden response to check whether it is good or not. [4]Memory is not composed of logic gates or flip-flops rather than these it is made up of a number of cells arranged in a symmetric manner As they have symmetry consumes less area than flip-flop or logic gates etc., Arranged in a compressed manner. Decrease in the memory price per bit due to quadrupled capacity every three years. High density implies decrease in size of capacitor used to store a bit (in experiments, it is found that if high dielectric capacity material is used in place of old ones like barium, tritium etc., Facility high capacitance maintained in less area) This memory cell only works to read and write these Cells as this cell comprises of 1 and 0 only. If we use flip-flop for memory building then we can observe it consumes more area with this it also not profitable in the market. Like general circuit, we do not discard faulty memory chips. Since every chip has defects so the faults are not only detected, but cell number is also diagnosed. [14] All memory cells will have a redundant circuit with them and it could be replaced by a faulty circuit. Capacitors are used to store bits if they charged they represent 1 if they are not they represents 0 values. Instead of the capacitor if flip-flops are used they lead to a very large area. The manufacturer builds some extra memory with the original one. Redundant circuit is switched by multiplexing arrangement or by blowing up with laser .

Memory cell

This is the unit which composed of a number of cells as they are arranged in a symmetric manner and it is a part where all RAM memory is present it holds value 1 and 0 in different cells, it has address bus and data bus in a parallel manner and they also have crossed arrangement of address and data bus, if address bus is active and it send 1 in data bus, the capacitor gets charged and shows 1 bit, and if in data bus we send 0 then its capacitor doesn’t charge and shows 0, in this manner we can write data or read data in the memory.

Decoders

Two types of Decoders are found in the memory as the name implies they work for decoding data they are Row Decoder and column decoder.
The Row or Column Decoder are Implemented using logic gates, as they are digital circuits, they together collect information of row and column and fetch data from where it is to be accessed.

Sense Amplifier

This is an analog circuit, this amplifier used to sense whether to read data or not if it senses the command of read instruction it fetches the data, it has two units different to read and write.

Driver

The Driver is used to writing data on cells.

MEMORY TESTING AND FAULT TYPES

As we know memory is made up of the combination cells, arranged in a sequential manner these cells may be affected by many reasons such as they could have manufacturing faults, operational faults etc. These faults fail the system to perform an accurate operation. The memory unit has four major parts
A Read/write logic,
An Address decoder
A Sense amplifier
The Memory cell,
When any of this part is affected may cause failure, so it becomes essential to test and remove the fault. Among them, a few are explained here.

Competition exam ....

It is very essential to work hard for competition exams..... but without interest no one could crack those exams .... there is always a reason behind them who become successful in those exams... some of them were hard worker and some are smart worker.... usually smarts are huge in this list.... coz we know boring work couldn't achieve anything...

To make things interesting i will add some tricky formulae and ways, and i will also tell you about things which are obstacles for us...

A engg student could know the level of education.... what is behind it and things which make study worst..... as i also experienced those things.... me 2 an engg student.... :)

@wareness

You know what this thing is?? Is it very important... is things are worthless without it.... yup this little word hold all the stuffs... this awareness could be the thing which can make you successful.. it may be or may not you 've heard about this tremendous word awareness... as this seems to be aware.... awaken... alive for surroundings.... yeah it mean the same....

I wont tell in detail because you are smart enough to understand this little things and alots if sources are available

To be cont....

Profit and loss

Buisness is a place where we always wann profit... but no one knows the result will be a loss or profit?? profit brings motivation and promote the buisness and that buisness person too.... but loss could also be possible....

Here important thing is that we need to know we are getting or loosing...
In mathematics we have formula to be aware...
Profit and loss always depends on the cost price we denote cost price as " C.P." and sell price as "S.P."

If S.P. is more than C.P. there will be profit

[Profit = S.P.- C.P.]

If C.P. is more

[Loss = C.P. - S.P.]

percentage is a value which is a part of 100 which shows how much you earned or loss by your buisness

Hence we need to know it..... the percentage of profit and loss always depends on cost price....

Profit% =  (Actual profit × 100 /  C.P.)

Loss % =  ( Actual loss × 100 / C.P. )

We can know selling price when there is a profit or loss and we already know the cost price..... 

BIST

BIST (Built in self test)

In the era of submicron technology memories may develop failure during the operation within their expected lifetime. The circuit needs to put on test mode and validates that whether it is free of fault or not, with the assumption that they would not damage within the expected life span, as the technology is shrinking assumption does not hold for the modern day. In the virtue of submicron technology to conquer such problem redundant circuitry kept on chips which replace the faulty part. It tests circuit every time before they start up. Module sensitizes the fault and propagates the effect to the output of CUT, It generates many patterns for 0 to 2^n if there are n flip-flops. The BIST a redundant circuit kept on the chip which replaces the erroneous circuit with the error-free part. Reduce power consumption is the main focus point of the project. mainly describe the equipment scan  be test edit itself in the circuit. In this additional software and hardware component are integrated on the board itself and there is no need of using the additional equipment to check the functionality and performance of the equipment, so by integrating the hardware and software will reduce the complexity of using external component of testing. the circuit will itself observe the performance BIST is used to test the complex circuit there are no external connections. It is the cheapest technique to implement the self test. Logic BIST implements most ATE function on chip so that the test cost can be reduced through less time less tester memory requirement or cheaper tester. Logic BIST applies large number of test patterns so that more defects can be detected. As LFSR and BIST are essential part of testing are executed at system clock modified LFSR is used which target to reduce power consumption, without affecting fault coverage and reduce switching transition we are able to reduce power consumption. Low correlation between test vector and switching activity leads to power dissipation. Hence modified LFSR help to reduce power leakage. 

#. Fault Modeling

• Real defects (often mechanical) too numerous and often not analyzable

• A fault model identifies targets for testing

• A fault model makes analysis possible

• Effectiveness measurable by experiments

Some Real Defects in Chips

• Processing defects 

• Missing contact windows

• Parasitic transistors

• Oxide breakdown

• Material defects

• Bulk defects (cracks, crystal imperfections)

• Surface impurities (ion migration)

• Time-dependent failures

• Dielectric breakdown

• Electro migration

• Packaging failures

• Contact degradation

• Seal leaks

When any of this part is affected may cause failure, so it becomes essential to test and remove the fault. Among them, a few are explained here.

1.... Stuck at Fault

A type of fault due to which cell does not change its state, it stuck at the previous state and become faulty, e.g. If any cell

Stuck at zero, it does not change its value from 0 to 1 it remains at 0. It stays in its state and this cause failure, due to this it doesn’t allow to fetch the accurate address or data value.

2..... Transition Faults 

Transition fault is a special type of stuck at fault in which at write operation, it fails to write 1 and  stay at its low state, hence it is called up transition fault, and if it unable to write 0 and stuck at 1 then this type of fat called us down transition fault. According to van de Goor [4] each cell must sustain an up transition (cell value goes from low to high) and a down transition (cell value goes from high to low) and be read after each transition before undergoing any further tra

3......Coupling Faults

Coupling faults are of three types [1].

• Inverse coupling fault: due to some reason changes in the value of one cell unexpectedly inverts the content of another cell. [13] 

• Idempotent coupling fault: a change in one cell forces an affix logic value of one cell into another cell. [13]

• State coupling fault: a cell is forced to a stay in its state only if the coupling cell/line is in a given state (pattern sensitivity fault (PSF)). [13]

4..... Bridging fault

The Bridging fault is a type of fat which is determined by its logical level instead of transition write operation because it is caused due to the short circuit between two or more cells. We have found three types of bridging faults [13]

....AND Bridging fault:

This is called so because the logical value of two faulty cells is AND of the two shortened cells acronym as ABF

.....OR Bridging fault:

This is called so because the logical value of two faulty cells is OR of the two shortened cells acronym as OBF.

6..... State Coupling fault

SCF is also a type of logical fault because a coupled cell is forced to certain value only because coupling cell is in that state

7...... Retention Faults (RF) 

A cell fails to regain its logic value after some time. This fault is caused by a broken pull-up resistor

8...... Neighborhood Pattern Sensitive 

The NPSF is a type of pattern sensitive fault in which cells are influenced by the neighboring cells; contents of cells are changed automatically by the transition of the neighboring cell from 0 to 1 or 1 to 0. Three types of NPSF faults are found: Active, Passive, and Static.

9..... Address Decoder Faults 

During the read-write operation (AFs) address decoder faults are the fault due to which decoders are not able to fetch accurate address to fetch data, to simplify such problems we consider a different system in which each cell are tested is called bit oriented memory. The Functional fault within the address decoder can be classified into four AFs For bit-oriented memories, because each cell is linked to a dedicated address, none of the faults listed above is individual. For example, when fault 1 occurs, then either fault 2 or fault 3 will occur as well. [4]

10..... Linked Faults 

Linked faults are more complex fault than the other faults explained in this paper in this type of faults many faults are linked with each other i.e. One fault occurs due to another one

11...... Data Retention Fault

Memory loses its content spontaneously not caused by read-write.

12.....Recovery Fault

When some part of memory may not recover fast enough from its previous state, Sense amplifier recovery: after reading, writing long string of 0s and 1s, write recovery: write followed by read or write in a different location resulting in reading or writing at the same location